In another post, I set up a basic Virtual Programming Lab exercise for RISC-V simulations with Assembler coding and the Kite simulator. That example is vulnerable to students hard-coding the register values without actually writing the necessary code. But I wrote it in order to provide a solid first example. Here, we're going to write […]
In this blog post I'm going to go through the steps for setting up a program for simulating basic RISC-V processors on computers in York University's EECS department. This should be helpful for undergraduate and graduate students, as well as faculty who want to use RISC-V in their research or courses. While we've been using […]
RISC-V processors, like ARM processors, are complex beasts, making them challenging to teach with. When teaching with them it's important to have appropriate development tools to reflect the immediate pedagogical goals but also to provide students with a pathway for further learning and application. When I teach courses on computer architecture, like EECS 2021 at […]
The Spike simulator is a command-line application for RISC-V development. It allows for both 32-bit and 64-bit simulations and supports multiple variants of RISC-V types. It's an alternative to using the Segger emSim simulator, which has both a graphical mode and a command line mode and. It's also more up-to-date and widely-used than the RVS […]
Introduction When I teach microprocessors to students I find it important to have access to good tools like simulators and IDEs. Up until now that hasn't been the case with RISC-V. Now that RISC-V tools are at a state that puts them on par with equivalent tools for AVR, ARM, x86, MIPS and PIC, I'm […]