simulator

RISC-V on EECS Dept Computers: Compiling and Simulating

In this blog post I’m going to go through the steps for setting up a program for simulating basic RISC-V processors on computers in York University’s EECS department. This should be helpful for undergraduate and graduate students, as well as faculty who want to use RISC-V in their research or courses. While we’ve been using […]

Simulated Microcontrollers in VPL Exercises

In Computer Architecture classes or Embedded Systems classes, it can be really useful to allow for students to be graded on assignments that allow them to interactively explore the inner workings of a microprocessor. One way is to have the students create programs in a hardware description language like Verilog or VHDL. Another way is […]